1. Field of the Invention
The present invention relates to a package structure of three-dimensional stacking dice and its manufacturing method. More particularly, the present invention relates to a wafer-level manufacturing method for fabricating the package structure of three-dimensional stacking dice.
2. Description of the Related Art
The three-dimensional integrated circuit package structure is generated due to the demand of electronic devices having lightweight and being thin, short and small. The Through-Silicon-Vias (TSVs) technology is employed to form vertical through holes in a silicon wafer, and filling insulating material and metallic material in the vertical through holes to form vertical electrical connection structures in the silicon wafer. Then, the silicon wafers are stacked together to form the three-dimensional integrated circuit package structure. This package structure has short electrical connection paths to avoid electricity problems happened in the electronic devices due to the increasingly shrinkage of the linewidth. This package structure also can increase the electrical transmission speed and is suitable for high-speed computation devices or memory devices. Moreover, this package structure is a kind of vertical stacking dice structure and can meet the demands of the electronic devices having lightweight, being thin, short and small as well as high-density package. The three-dimensional integrated circuit stacking structure has become a primary advanced package structure in the future.